The proliferation of modern electronics is due in large part to the development of the integrated circuit. Integrated circuits allow many different circuit elements to be implemented on a single microchip. As technology advances, the number of circuit elements on a microchip continues to increase, which enhances the performance and reduces the cost of integrated circuits.
The design of integrated circuits is typically performed in three stages. The first stage includes logic design, where the desired operation of the integrated circuit is defined. The second stage, logic synthesis, involves translating the desired operation into the required circuit elements for a given technology. The third stage is physical design, which assigns the placement of these elements. Physical design also determines routing, which creates the wire interconnect of these elements on the integrated circuit.
Integrated circuits have traditionally been characterized by the clock frequency at which they operate. Gauging the ability of a circuit to operate at the specified speed requires the ability to measure its delay at numerous steps during the design process. Moreover, delay calculation must be incorporated into the inner loop of timing optimizers at various phases of the design, such as logic synthesis, layout (placement and routing), and in in-place optimizations performed late in the design cycle.
Some logic designs contain complex delay elements whose delay is a function of the state of the logic, rather than just a static value. In a synchronous digital system, data is supposed to move in lockstep, advancing one stage on each tick of the clock signal. This is enforced by synchronizing elements such as flip-flops or latches, which copy their input to their output when instructed to do so by the clock.
Many of the common problems in chip design relate to interface timing between different components of the design. The time when a signal arrives can vary for many reasons. For instance, the input data may vary, and/or the circuit may perform different operations. The temperature and voltage may change, the clock signal may be at an optimized frequency, and/or there may be manufacturing differences in the exact construction of each part. Other problems may stem from the simulation model being incomplete, or there may be a lack of test cases to properly verify interface timing. Synchronization requirements may vary, and/or there may be incorrect interface specifications, among other considerations.
Examples of problems that can occur from poor timing include a hold time violation, when a signal arrives too early and advances one clock cycle before it should. Another problem includes a setup time violation, when a signal arrives too late and misses the time when it should advance.
At the logic synthesis stage of integrated circuit design, a static timing tool is typically used to perform a static timing analysis to compute the expected timing of a digital circuit without requiring simulation. Static timing analysis generally takes into account best-case and worst-case delays of various circuit elements, thereby generating a list of problems that need to be corrected. As such, static timing analysis plays a vital role in facilitating the fast and reasonably accurate measurement of circuit timing.
The main goal of static timing analysis is to verify that despite possible variations, all signals will arrive neither too early nor too late, and hence proper circuit operation can be assured. In static timing analysis, the word static alludes to the fact that the timing analysis is carried out in an input-independent manner, and purports to find the worst-case delay of the circuit over all possible input combinations.
As previously stated, behavior of an electronic circuit is often dependent on various, variable factors in its environment. In such a case, either static timing analysis needs to be performed for more than one such set of conditions, or it must be prepared to work with a range of possible delays for each component, as opposed to a single value. If the design works at each extreme condition, then under the assumption of monotonic behavior, the design is also qualified for all intermediate points.
EinsTimer, developed by International Business Machines Corp. (IBM), uses a statistical engine to apply static timing analysis to critical paths in designs in order to derive models that are more silicon-accurate than most models used in static analysis. The models derived from the EinsTimer tool can then be applied to the rest of the paths in the design, improving the design's overall performance over traditional static timing analysis. Performance gain obtained will depend upon the chip and the length of paths on the chips.
EinsTimer additionally accounts for sources of variation and how the cells in the library have delays that depend on these process parameters. A characterization tool is used that analyzes every cell in the library to understand the sensitivity of cell delays to process. The characterization tool then outputs a modified library file that is used by the statistical tool for analysis. Reports and yield plots are also output in order to help users to better understand their design. For example, users can employ the tool after they have routed their design and created a clock tree in order to understand sensitivity to metal issues and transistor parameters. This feature provides designers with an idea of how robust their design is, and thus, what kind of yield to expect on a particular design. The design can then be modified to improve these timing characteristics prior to tapeout.
While the EinsTimer and other static timing analysis tools provide valuable information and are useful in the design of integrated circuits, these processes currently require significant amounts of processing and memory resources. For instance, a designer may wish to model the effects of multiple clock signals in a timing run. In one example, it may be desirable to see the affects of using clock signals with multiples of the same frequency. As such, different clock signals must be generated individually for use in modeling. Each individually generated clock signal, or phase, must then be separately modeled in a static timing analysis run. The generation and modeling phases can consume a considerable amount of the designer man-hours and computer resources.
Therefore, what is needed is a way to generate and analyze timing data in a manner that minimizes the computing resources, time or money costs conventionally associated with static timing analysis.